--
-- vhdl architecture fietscomputer_lib.fc_ontdender.ontdender
--
-- created:
--					by - 10070052.demi staal (dtp7797)
--					at - 11:55:54 29-09-2011
--
-- using mentor graphics hdl designer(tm) 2008.1b (build 7)
--
library ieee;
use ieee.std_logic_1164.all;

entity fc_ontdender is
	port (
		knopje : in	std_logic;
		clk : in std_logic;
		rst : in std_logic;
		
		ontknopje : out std_logic		
	);
end fc_ontdender;
	
architecture ontdender of fc_ontdender is
	signal counter		: natural range 0 to 2000;
	signal running : std_logic;
	signal synchronize : std_logic_vector(1 downto 0);
begin
		
	process(rst,clk)			
	begin
		if rst = '1' then
			ontknopje <= '0';
			counter <= 0;
			running <= '0';
			synchronize <= (others => '0');
		elsif rising_edge(clk) then
			-- Double synchronize input signal
			synchronize(1) <= synchronize(0);
			synchronize(0) <= knopje;
			
			-- Default 0
			ontknopje <= '0';
			
			-- Check for rising edge
			if synchronize(0) = '1' and synchronize(1) = '0' then
				if counter >= 300 then
					counter <= 0;
					running <= '0';
					
					ontknopje <= '1';
				end if;
			end if;						
			
			if counter >= 2000 then
				counter <= 0;
				running <= '0';
			else
				if running = '0' then
					if synchronize(1) = '0' then
						counter <= 0;
						running <= '1';
					end if;
				else
					counter <= counter + 1;
				end if;
			end if;	
		end if;
	end process;
end architecture ontdender;